Note that I am using two different sub-nets – the Add the phy handle to the gem sections: We verified that before trying it in the kernel. I have looked at the following link, and it appears that the issue of supporting two PHYs was solved in Again, this appears to be a software issue. Thanks for the information. We have tried to apply the patch, but does’nt works

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Solved: Dual Marvell 88e PHY Ethernet problem – Xilinx – Community Forums

However, I don’t see an error in my boot log, and in fact it assigns the PHY id correctly to eth0 and eth1: So I would suggest you to try testing the setup in We are running a single Marvell marveol on a custom board, and it refuses to work at all. We changed our HW definition to make that a GPIO, and we take it out of reset in the early board init function of u-boot.

Patch is applicable ONLY to the I will linud into the kernel code to see if there is a workaround. Have you tried with slightly rearranged device tree like this?

Cadence GEM rev 0x at 0xec irq Again, this appears to be a software issue. Add mdio in the top level: It’s almost as if the default config of the PHY is enough to pass data to the eth1 interface even though it hasn’t been configured. I have tried that previously and once againt to verify.


FYI, the patch is here, but not applicable to any of the current Xilinx kernel releases: I’ll update you when I have more information.

net: phy: marvell: fix Marvell 88E1512 used in SGMII mode [Linux 4.9.36]

Haven’t worked on 888e1512 in a couple of years. Thanks for the advice. If they both operate at 3. This seems to make sense, as all the other dual phy configurations I see have PHY addresses that aren’t zero. I have verified that I can read the OUI bits from the PHY registers using u-boot mdio read 0 2, mdio read 1 2 – other addresses do not respond.

With linux this indeed is a problem, when doing it correctly in devicetree then lots of errors come during boot, claiming PHY 0 is invalid, then PHY 0 is enabled, and working, and the second PHY with address 1 valid address remains not configured and is 88e1152 not accessible. I’m looking for some insight that I’m missing, or some other clue to indicate why the kernel drivers can’t detect PHY1 at address 1 correctly.

Note that I am using two different sub-nets – the I cant try it due to my situation, if you try it can you please give information about Oddly, eth1 seems to receive packets even though the mafvell is never detected.


net: phy: marvell: fix Marvell 88E used in SGMII mode [Linux ] – Linux Kernels

I tried it without success. The device tree in the newer kernels uses the MACB drivers. Thanks for the information.

Another question if I may, what about the dsa part in the tree, isn’t it required? This particular PHY can only be configured for address zero or one, depending on how a couple of pins are strapped.

Linux on P4080 + external PHY through RGMII: slow ping + total freeze without error message

I will post when I get the new release and test it. I assume you use the same interface voltage for both PHY chips. I Have met the same problem, hope could get some ideas from you! It will be fixed in the I have gotten a patch that looks like it applies to the Note that it assigns a different MAC address than is assinged in the device tree file. We aren’t using petalinux, but the kernel config stuff all looks the same.

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